What is TLB?
TLB stands for Translation Look-aside Buffer. It is a cache on the CPU which is used to speedily translate virtual addresses to real addresses. In its normal implementation, TLB uses CAM or content-addressable memory to serve as the virtual address and the physical or real address will be the search result. Normally what happens is that the CAM will search for a match for the address translation. If a match is found, then the information or data is used. Otherwise, in cases where no matches can be found by the CAM search, the address translation will continue the process by using page tables. This part of the process usually takes a couple of cycles before completion. But with TLB, the processing and translation of addresses is speedier because this particular process will work on its own and is independent from the other activities like typical address translations in the pipeline.

TLB contains slots that have the page tables in them. These slots are fixed in number. What the page table entries do is to map out virtual forms of addresses into real addresses. But depending on location of the TLB, the cache may use real or virtual addresses. TLBs may be positioned somewhere in between the cache of the CPU and the CPU itself. Or it may also reside in between the primary storage memory and the cache of the particular CPU. In this setup, the CPU will only use TLB or do a TLB lookup if the CPU cache is addressed physically. The search result or the real address will then be sent back to the cache afterwards. On the other hand, in virtual addressing, requests pass through directly from the CPU to the CPU cache, without accessing the TLB except for instances like a cache miss.

TLB is said to be the first cache system used in computer processors. Newer computers of today typically use TLB on their respective processors. TLBs can also be used and implemented in multiple levels, just like the basic CPU caches.